About the role
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:As a member of the Infinity Fabric Architecture and RTL team, you will design and implement key components of a scalable, coherent on-chip network that enables high-speed communication across CPUs, GPUs, and accelerators. This role focuses on defining microarchitecture and developing RTL for interconnect (NoC/fabric) subsystems that support a wide range of products including servers, AI platforms, client devices, and gaming systems. You will work closely with cross-functional teams across Austin and global sites to deliver high-quality, performance-optimized hardware in a collaborative, fast-paced environment. The Person:You are an experienced RTL design engineer with a passion for complex processor systems and interconnect architecture. You bring deep technical expertise, a structured problem-solving approach, and the ability to design, debug, and optimize hardware effectively. You thrive in collaborative, multi-site environments, communicate clearly with cross-functional teams, and take ownership of your work. You are also open to leveraging modern tools, including AI-assisted approaches, to improve design quality and productivity. Key Responsibilities:Define microarchitecture for interconnect (fabric / network-on-chip) componentsDevelop and implement synthesizable RTL using Verilog/SystemVerilogOptimize designs to meet power, performance, area, and timing goalsContribute to scalable, coherent interconnect solutions across multiple product linesCollaborate with architecture, verification, and cross-functional engineering teamsSupport unit-level validation and deliver high-quality RTL to verification teamsDevelop assertions and contribute to coverage strategiesDebug design issues during pre-silicon and post-silicon phasesCreate clear and maintainable design documentationPreferred Experience:Experience with RTL design using Verilog or SystemVerilogBackground in interconnect, network-on-chip (NoC), or cache/memory subsystem designUnderstanding of processor architecture, including coherency and memory systemsKnowledge of digital design fundamentals and high-speed hardware systemsExperience debugging RTL or hardware systemsFamiliarity with power, performance, and area tradeoffsExposure to scripting or programming languages such as Python, C, or C++Awareness of design-for-test (DFT) conceptsFamiliarity with x86 or ARM architectures is helpfulInterest in using AI-assisted tools to improve design and debugging workflowsAcademic Credentials:BS, MS, or PhD degree in Electrical or Computer engineering preferred. This role is not eligible for Visa Sponsorship. #LI-LC3#LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. The Role:As a member of the Infinity Fabric Architecture and RTL team, you will design and implement key components of a scalable, coherent on-chip network that enables high-speed communication across CPUs, GPUs, and accelerators. This role focuses on defining microarchitecture and developing RTL for interconnect (NoC/fabric) subsystems that support a wide range of products including servers, AI platforms, client devices, and gaming systems. You will work closely with cross-functional teams across Austin and global sites to deliver high-quality, performance-optimized hardware in a collaborative, fast-paced environment. The Person:You are an experienced RTL design engineer with a passion for complex processor systems and interconnect architecture. You bring deep technical expertise, a structured problem-solving approach, and the ability to design, debug, and optimize hardware effectively. You thrive in collaborative, multi-site environments, communicate clearly with cross-functional teams, and take ownership of your work. You are also open to leveraging modern tools, including AI-assisted approaches, to improve design quality and productivity. Key Responsibilities:Define microarchitecture for interconnect (fabric / network-on-chip) componentsDevelop and implement synthesizable RTL using Verilog/SystemVerilogOptimize designs to meet power, performance, area, and timing goalsContribute to scalable, coherent interconnect solutions across multiple product linesCollaborate with architecture, verification, and cross-functional engineering teamsSupport unit-level validation and deliver high-quality RTL to verification teamsDevelop assertions and contribute to coverage strategiesDebug design issues during pre-silicon and post-silicon phasesCreate clear and maintainable design documentationPreferred Experience:Experience with RTL design using Verilog or SystemVerilogBackground in interconnect, network-on-chip (NoC), or cache/memory subsystem designUnderstanding of processor architecture, including coherency and memory systemsKnowledge of digital design fundamentals and high-speed hardware systemsExperience debugging RTL or hardware systemsFamiliarity with power, performance, and area tradeoffsExposure to scripting or programming languages such as Python, C, or C++Awareness of design-for-test (DFT) conceptsFamiliarity with x86 or ARM architectures is helpfulInterest in using AI-assisted tools to improve design and debugging workflowsAcademic Credentials:BS, MS, or PhD degree in Electrical or Computer engineering preferred. This role is not eligible for Visa Sponsorship. #LI-LC3#LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.