SystemVerilog jobs
2 live openings · Programming Languages
C
ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)Cisco · Pune, India · 2 months
C
ASIC Engineering Technical Leader | RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) | Exp - 12+ yearsCisco · Bangalore, India · 2 months